Hold time violations are to be found in industrial designs for different reasons. For instance, in a shift register, hold time violations occur when the clock skew is bigger than the clock-to-data output pin-to-pin timing of some flip-flops. As an example FIG. 1A shows a shift register comprising two flip-flops 10 and 12. In this FIG. 1A a clock skew is modeled as a delay cell 14.
In multiphase designs, hold time violations occur when some phase conditions are not respected between the different clocks. Such a case is shown in FIG. 2A in which two different clock signals ck.sub.1 and ck.sub.2 are provided to flip-flops 11 and 13. Hold time violations also occur on external input connectors to internal register timing paths when these paths are smaller than the clock latency, defined as the delay between the external clock connector and the register clock connector. Such a case is shown in FIG. 3a in which the delay is modeled as delay cell 16 which delays a clock signal provided to a sequential gate 18.
Generally hold time violations can be fixed, i.e. eliminated, by working on the clock network or on the clock itself. For instance, the hold time violation present in the shift register of FIG. 1A can be fixed by reducing the clock skew below the flip-flop clock-to-data output pin-to-pin timing by using a clock tree synthesis tool. Such a synthesis tool is described for example in "A Hierarchical Clock Tree Synthesizer," written by A. Ginetti et al. in "EuroAsic 94," Paris, hereinafter "document (1)". The hold time violations due to the bad clock phase difference ck.sub.2 -ck.sub.1 of FIG. 2A can be fixed by revisiting the clock wave forms, or by delaying one of the clocks inside the design. The hold time violations introduced by the too long clock latency can be overcome by using a very fast clock tree (see document (1)) or by using a giant pad buffer or even by using a PLL (Phase Locked Loop). Unfortunately all these solutions have their limitations: for instance, it is impossible to decrease the clock skew below a certain level, or some giant pad buffers are too slow to drive thousands of flip-flops, and PLL are not always available.
Hold time violations can also be fixed by working on the data signals, or more exactly by slowing down these data signals: for instance, the hold time violation introduced by the clock skew in the shift register of FIG. 1A can be fixed by slowing down the signal creating this violation. FIG. 1B shows an example in which the violation is fixed by a delay cell connected between the data output connector of flip-flop 10 and the data input connector of flip-flop 12. The same solution applies for fixing the hold time violation present in the multiphase design of FIG. 2A and the one introduced by the big clock latency 16 in the case of FIG. 3. As shown in FIGS. 2B and 3B delay cells 22 and 24 have respectively been introduced in the designs of FIGS. 2A and 3A.
For a better understanding of the following sections, the meaning of a timing constraint is hereafter briefly explained.
A timing constraint is a way to specify a delay between nodes in a design. The specified delay can be a minimum delay or a maximum delay. When the specified delay is a minimum delay, one speaks of minDelay timing constraint or lower-bounded timing constraint. When the specified delay is a maximum delay, one speaks of maxDelay timing constraint or upper-bounded timing constraint.
More accurately, a maxDelay timing constraint is composed of:
a set of input nodes; PA1 a set of output nodes; PA1 for each input node, a signal maximum arrival time, that is the latest time at which the signal is available on that node; PA1 for each output node, a signal maximum required time, that is the latest time at which the signal should be available on that node; and, a minDelay timing constraint is composed of: PA1 a set of input nodes; PA1 a set of output nodes; PA1 for each input node, a signal minimum arrival time, that is the earliest time at which the signal is available on that node; PA1 for each output node, a signal minimum required time, that is the earliest time at which the signal should be available on that node. PA1 for checking that a design meets certain performance requirements; PA1 for guiding performance driven optimization tools. PA1 the environment world of a design usually imposes arrival times on external input connectors and required times on output connectors; PA1 the clock frequency and phase usually imposes arrival times on sequential element data output and required time on sequential element data input connectors; PA1 a desired clock latency usually imposes arrival times (respectively required times) on the clock network input node (respectively output nodes). PA1 ff1 will be called the master flip-flop; PA1 ff2 will be called the slave flip-flop; PA1 ck1 will be called the master clock; PA1 ck2 will be called the slave clock; PA1 the shortest combinational path between ff1 data output connector to the ff2 data input connector will be called shortest path; this path is actually composed of the ff1 ck1-to-q timing plus the combinational path minus the ff2 hold time; PA1 the longest combinational path between ff1 data output connector to the ff2 data input connector will be called the longest path; this path actually is composed of the ff1 ck1-to-q timing plus the combinational path plus the ff2 set-up time. PA1 a data fired by the master clock active edge that follows the set-up launch edge must not be latched by the set-up latch edge; PA1 a data fired by the set-up launch edge must not be latched by the slave clock active edge that precedes the set-up launch edge. PA1 a set-up multiplier which usually is the number of slave active edges to be added to the default set-up latch edge for set-up checking; the clock is not multicycled, the default number is obviously one. To sum up, setting a set-up multiplier of "n" consists in pushing forward the set-up latch edge by an amount of "n-1" slave clock cycles. The set-up multiplier can also be specified as the number of master active edges to be removed from the default set-up launch edge. In this case, setting a set-up multiplier of "n" consists in pushing backward the set-up launch edge by an amount of "n-1" master clock cycles; PA1 a hold multiplier which usually is the number of master active edges to be added to the default detected hold set-up edge. The default number is zero, whether the slave clock is multicycled or not. To sum up, setting a hold multiplier of "n" consists in pushing forward the set-up launch edge by an amount of "n" master clock cycles. The hold multiplier can also be specified as the number of slave active edges to be removed from the set-up latch edge; in this case, setting a hold multiplier of "n" consists in pushing backward the set-up latch edge by an amount of "n" slave clock cycles. PA1 a list of input node names; PA1 a list of input node arrival times; PA1 a list of output node names; PA1 a list of output node required times. PA1 the list of nodes to be specified is "design-specific", i.e. the list of nodes contains the names of the sequential element clocked on the clock. It is unlikely that the user will be able to specify the complete list of all these sequential elements without omitting one; PA1 the list of nodes to be specified is "technology specific", i.e. the list of nodes contains the name of the data connector of the sequential elements, like "q", "qn", "d", "da", "db", "s". PA1 1) synthetizing a RTL-HDL type description of the circuit to form a synthesized design, PA1 2) synthetizing a clock tree and adding it to the synthesized design produced in step 1, PA1 3) optimizing the synthesized design resulting from step 2 and fixing upper-bounded timing constraints by using a real clock timing (latency and skew) and worst case conditions, PA1 4) fixing lower bounded timing violations in the optimized synthesized design resulting from step 3, using a real clock timing, using best case conditions, PA1 5) re-fixing possible newly created upper-bounded timing constraints and possible upper-bounded timing constraints increased in step 4, PA1 6) fixing post-layout upper-bounded timing violations. PA1 a logic optimizer, for fixing upper-bounded timing violations of the circuit and optimizing an area of said circuit, PA1 a clock tree synthesizer, (see document (1)), PA1 a lower-bounded timing violation fixer, PA1 a post-layout upper-bounded timing violation fixer.
Timing constraints are used for at least the two following reasons:
Checking a timing constraint consists in propagating timing constraint input node arrival time along the design and comparing the value of the propagated time and the required time on the output node. For maxDelay timing constraint, the "slack" is defined as the difference between the required time and the arrival time. For minDelay timing constraint, the "slack" is defined as the difference between the arrival time and the required time. A design is said to be violating a timing constraint when at least one of the timing constraint output node slack is negative. The worst path of a timing constraint is the path ending on the timing constraint output node the slack of which is the smallest. Guiding a performance driven optimization tool consists in providing it with the user design and timing constraints and asking said tool to optimize the design in order to meet these timing constraints.